In any power amplifier (PA) system, a saturation condition can occur where the target power (desired power) is beyond the capability of the PA under the conditions at a given instant of time. If the target power level is not reduced under these conditions, then the control system of the PA will enter a state where the PA system will not respond to accurate power control on a timely basis. This will result in violation of spectral purity and may result in damage to the PA.
FIG. 1 illustrates a conventional power amplifier (PA) system powering up, reaching saturation, and “winding up.”
In FIG. 1, Vramp is a control signal set at the desired output voltage of the power amplifier. Vapc is an integration control system voltage, which will be discussed in more detail later. SATURATION INDICATOR is a saturation flag that reads 1 volt when the PA is saturated, and read 0 volts when the PA is not saturated.
In FIG. 1, Vramp ramps from 0 volts to 1.5 volts. SATURATION INDICATOR indicates that the PA is saturated at 64 qs, and stays saturated afterwards. Control signal Vapc follows Vramp relatively closely until after saturation occurs at 64 qs, and then continues increasing until a maximum value of 2.5 volts (a “wind up” voltage) is reached. (A “qs” is a standard unit of time in telecommunications, and is equivalent to about 3.69 microseconds.) This excessively high Vapc voltage creates many problems.
In other words, the control system of the PA will continue to increase the drive to the PA in an attempt to balance the integrator inputs of the control system, even when these attempts are no longer having any additional effect on the PA. For example, the voltage to the PA has been driven up to the battery voltage, so any additional increases in Vapc have no effect on the power of the PA. This situation is most likely at high temperature and low battery voltage, wherein the maximum PA output power is small. The term “battery voltage” is used in this specification and claims broadly to refer to a power supply voltage, from a battery or from some other source.
FIG. 2 illustrates a saturated PA system winding down. In FIG. 2, Vramp begins at 1.5 volts, and smoothly drops to about 0.3 volts. The SATURATION INDICATOR flag indicates that the PA stops being saturated at 656 qs. However, the integration control system voltage Vapc unfortunately begins at a “wind up” voltage of 2.5 volts, and then violently starts dropping at 659 qs as the control system tries to follow Vramp.
In other words, during this “ramp down” period, the integrator has to “un-wind” (discharge its capacitors) before the actual ramp down can begin. Then the integrator has to try to catch up with the decreasing Vramp, and the result is a poorly shaped Vapc curve that causes switching spectrum problems. Note the delay on the Vapc curve, where from 657 qs to 659 qs the Vapc stays at 2.5 volts even though Vramp has already started ramping downward. This delay is typically caused by the need to discharge capacitors that have been wound up due to saturation problems.
FIG. 3 illustrates the effect of saturation on the PA output power during a ramp down, starting at a saturated power level of approximately 32 dbm. In FIG. 3, the ideal power curve smoothly drops, starting at 657 qs. In contrast, the measured power curve does not begin dropping until 661 qs, indicating a delay of about 4 qs as the capacitor in the control circuit discharges. Additionally, the measured power turns downward very sharply (violently) from 661 to 663 qs, in comparison with the smooth ideal power curve. This sharp turn causes many problems.
FIG. 4 illustrates a switching spectrum with an ETSI (European Telecommunications Standards Institute) violation. In FIG. 4, the ramp curve ramps up at about 70 qs, then ramps down at about 670 qs. The ETSI Limit (horizontal line) indicates that the spectral content should not exceed a maximum of −22 dBm.
The −400 kHz Ideal and the +400 kHz Ideal curves indicate ideal curves offset by +/−400 kHz from a carrier frequency of 900 MHz. The real −400 kHz and the real +400 kHz curves indicate the actual (non-ideal) spectrum.
At point A, the real −400 kHz and the real +400 kHz curves both have high peaks at 690 qs that exceed the ETSI Limit. These undesired high peaks illustrate the problems caused by ramping down from a “wound up” integration control system.
The above discussion of FIGS. 1-4 was presented for a closed loop system with an integration control system. Similar problems occur for an open loop system that controls output power with a collector supply voltage. In this open loop system, there is no integrator to “wind-up” to the supply voltage, but instead there is a large PFET (with substantial internal capacitance) that will drive to zero a drain to source voltage, and will still wind-up (although to a lesser extent than a closed loop system).